The present technique relates to the determining of address translation data to be stored within an address translation cache.
It is known to provide data processing systems which incorporate an address translation cache, such as a translation lookaside buffer (TLB), to store address translation data relating to the translation of, for example, virtual addresses to physical addresses. The address translation data can also provide attribute data regarding the memory accesses being made, such as permission data and memory attributes. Whilst the provision of an address translation cache is useful in improving performance by reducing the number of slow page table walks required, such an address translation cache can occupy significant circuit resources, and accordingly it is desirable to make efficient utilisation of those resources.
Each entry in the address translation cache may provide address translation data for a page in memory. There are a number of known software techniques that can be used to form larger pages, but situations where such techniques can be used are often limited. Whilst page aggregation can instead be performed in hardware to seek to overcome such limitations, known hardware techniques can impact latency in the handling of requests issued to the address translation cache by associated circuitry, for example a processor core. It would hence be desirable to provide an improved mechanism for allowing more efficient utilisation of entries in the address translation cache.